Transistor and method of manufacturing the same

ABSTRACT

A transistor includes source region and drain regions, a channel region, a drift region, a gate, a dummy gate, a gate dielectric layer and an interconnection line. The source and drain regions of a first conductivity type are in a substrate. The channel region of a second conductivity type is in the substrate and surrounds the source region. The drift region of the first conductivity type is beneath the drain region and extends toward the channel region. The gate is over the substrate and overlapped with the channel region and the drift region. The dummy gate is over the drift region and laterally adjacent to the gate. The gate dielectric layer is between the gate and the substrate and between the dummy gate and the drift region. The interconnection line is electrically connected to the dummy gate and configured to provide a voltage potential thereto.

BACKGROUND

Power semiconductor devices including high-voltage integrated circuits(ICs) are currently being used in many applications. The high-voltageICs that typically include high voltage metal-oxide-semiconductor (MOS)transistors are widely used in applications like automobile industry,display drivers, portable telecommunication devices and medicalequipment.

A commonly used high-voltage MOS transistor for the high-voltage ICs isa laterally diffused MOS (LDMOS) transistor. The LDMOS transistor oftenpossesses high breakdown voltage and thus can be utilized for thesehigh-voltage applications. However, the higher the breakdown voltage ofthe LDMOS transistor typically scarifies the device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a cross-sectional view of a general transistor.

FIG. 2 is a cross-sectional view of a general transistor.

FIG. 3 is a cross-sectional view of a general transistor.

FIG. 4 is a cross-sectional view of a general transistor.

FIG. 5 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure.

FIG. 6 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure.

FIG. 7 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure.

FIG. 8 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure.

FIG. 9 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure.

FIGS. 10A-10F are cross-sectional views at various stages ofmanufacturing a transistor in accordance with some embodiments of thepresent disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

As mentioned above, the higher the breakdown voltage, the worse thedevice performance is. In contrast, the better the device performance,the worse the breakdown voltage is, which is related to devicereliability. That is, the device performance and the device reliabilityare trade off.

FIGS. 1-4 are cross-sectional views of general transistors. As shown inFIG. 1, a transistor 10 includes a source region SR, a drain region DR,a channel region 112, a drift region 114, a gate G, a gate dielectriclayer 122 and a protective layer 140. The channel region 112 and thedrift region 114 are in a substrate 110. The source region SR and thedrain region DR are respectively in the channel region 112 and the driftregion 114. The gate G, the gate dielectric layer 122 and the protectivelayer 140 are over the substrate 10. The transistor 10 may provide highdrain current but exhibit low time dependent dielectric breakdown (TDDB)and device breakdown since drain field may be directly penetrated to anedge of the gate G when the transistor 10 is at an off state, whichresults in poor device reliability.

As shown in FIG. 2, a transistor 20 includes a source region SR, a drainregion DR, a channel region 112, a drift region 114, a gate G, a gatedielectric layer 122, a protective layer 140 and an isolation region160. The isolation region 160 may be a shallow-trench isolation (STI)region or a field oxide (FOX) region. The transistor 20 can provide gooddevice reliability due to the presence of the isolation region 160, butexhibits very poor device performance due to long drain current path.

As shown in FIG. 3, a transistor 30 includes a source region SR, a drainregion DR, a channel region 112, a drift region 114, a gate G, afloating dummy gate FDG, a gate dielectric layer 122 and a protectivelayer 140. The floating dummy gate FDG is designed to prevent currentpassing near a surface of the drift region 114 and to increaseresistance of the drift region 214 when the transistor 30 is at onstate. However, when the transistor 30 is at off state, drain field maybe directly penetrated to an edge of the gate G. In order to meetrequirements of device reliability, a length of the drift region 114 orthe gate G should be increased, which is unfavorable to device size anddevice performance.

As shown in FIG. 4, a transistor 40 includes a source region SR, a drainregion DR, a channel region 112, a drift region 114, a gate G, afloating dummy gate FDG, a gate dielectric layer 122, a protective layer140 and a counter implant region 170. The difference between thetransistors 30, 40 of FIGS. 3-4 is that the transistor 40 furtherincludes the counter implant region 170 designed to suppress drain fieldand thus to improve device reliability when the transistor 40 is at offstate. However, device performance is poor when the transistor 40 is aton state due to long drain current path. In addition, there is a needfor an additional mask for forming the counter implant region 170, whichrequires extra cost.

In view of the foregoing, the present application provides a transistorincluding a source region, a drain region, a channel region, a driftregion, a gate, a dummy gate, a gate dielectric layer and aninterconnection line. The interconnection line is electrically connectedto the dummy gate and configured to provide a voltage potential to thedummy gate. The dummy gate receiving the voltage potential is configuredto let drain current pass near a surface of the drift region, and thusto significantly increase drain current and improve device performancewhen the transistor is at on state. Embodiments of the transistor and amethod for manufacturing the transistor will be sequentially describedbelow in detail.

FIG. 5 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure. The transistor 50 includes asource region SR, a drain region DR, a channel region 212, a driftregion 214, a gate G, a dummy gate DG1, a gate dielectric layer 222 andan interconnection line 250.

The source region SR and the drain region DR are of a first conductivitytype and in a substrate 210. In some embodiments, the substrate 210includes an elementary semiconductor including silicon or germanium incrystal, polycrystalline, or an amorphous structure; a compoundsemiconductor including silicon carbide, gallium arsenide, galliumphosphide, indium phosphide, indium arsenide, and indium antimonide; analloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs,GaInP, and GaInAsP; any other suitable material; or combinationsthereof. In some embodiments, the substrate 210 is an n-type or p-typesemiconductor substrate. In some embodiments, the transistor 50 is ann-type transistor, and the substrate 210 is a p-type semiconductorsubstrate. In some embodiments, the transistor 50 is a p-typetransistor, and the substrate 210 is an n-type semiconductor substrate.In some embodiments, each of the source region SR and the drain regionDR has a dopant concentration ranging from about 10 ¹⁸ ions/cm³ to about10 ²⁰ ions/cm³.

The channel region 212 of a second conductivity type opposite to thefirst conductivity type is in the substrate 210 and surrounds the sourceregion SR. In some embodiments, the transistor 50 is an n-typetransistor, and the channel region 212 includes p-type dopants, such asboron, boron difluoride, or another suitable p-type dopants or acombination thereof. In some embodiments, the transistor 50 is a p-typetransistor, and the channel region 212 includes n-type dopants, such asphosphorus, arsenic, antimony, bismuth, selenium, tellurium, anothersuitable n-type dopants or a combination thereof.

The drift region 214 of the first conductivity type is beneath the drainregion DR and extends toward the channel region 212. In the embodimentsshown in FIG. 5, the drift region 214 is separated from the channelregion 212. In other embodiments, the drift region is laterally adjacentto and in contact with the channel region. In some embodiments, thetransistor 50 is an n-type transistor, and the drift region 214 includesn-type dopants, such as phosphorus, arsenic, antimony, bismuth,selenium, tellurium, another suitable n-type dopants or a combinationthereof. In some embodiments, the transistor 50 is a p-type transistor,and the drift region 214 includes p-type dopants, such as boron, borondifluoride, or another suitable p-type dopants or a combination thereof.

The gate G is over the substrate 210 and overlapped with a portion ofthe channel region 212 and a portion of the drift region 214. In someembodiments, the gate G is a single layer structure or a multi layerstructure. In some embodiments, the gate G includes metal, alloy,ceramet, ceramal or a combination thereof. The term “ceramet” refers toa composite material composed of ceramic and metallic materials. Theterm “ceramal” refers to a composite material composed of ceramic andalloy materials. In some embodiments, the gate G includes titanium (Ti),tantalum (Ta), tungsten (W), aluminum (Al), zirconium (Zr), hafnium (Hf)or a combination thereof. In some embodiments, the gate G includespolysilicon or another suitable materials. The material of the gate Gmay be selected in accordance with the conductive type (i.e., n-type orp-type) of the transistor 50.

The gate G has a work function. The term “work function” refers to theminimum energy (usually expressed in electron volts) needed to remove anelectron from a neutral solid to a point immediately outside the solidsurface (or energy needed to move an electron from the Fermi energylevel into vacuum). Here “immediately” means that the final electronposition is far from the surface on the atomic scale but still close tothe solid surface on the macroscopic scale.

The dummy gate DG1 is over the drift region 214 and laterally adjacentto the gate G. In some embodiments, the dummy gate DG1 is a single layerstructure or a multi layer structure. In some embodiments, the dummygate DG1 includes metal, alloy, ceramet, ceramal or a combinationthereof. In some embodiments, the dummy gate DG1 includes titanium (Ti),tantalum (Ta), tungsten (W), aluminum (Al), zirconium (Zr), hafnium (Hf)or a combination thereof. The material of the dummy gate DG1 may beselected in accordance with the conductive type of the transistor 50.

In some embodiments, the dummy gate DG1 includes metal, such as titanium(Ti), tantalum (Ta), tungsten (W), aluminum (Al), zirconium (Zr),hafnium (Hf) or other suitable metals. In some embodiments, the dummygate DG1 includes alloy, such as titanium aluminum (TiAl), tantalumaluminum (TaAl), tungsten aluminum (WAl), zirconium aluminum (ZrAl),hafnium aluminum (HfAl), a combination thereof or other suitable alloys.In some embodiments, the dummy gate DG1 includes ceramet, such astitanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride(TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride(WSiN), titanium carbide (TiC), tantalum carbide (TaC), a combinationthereof or other suitable ceramets. In some embodiments, the dummy gateDG1 includes ceramal, such as titanium aluminum carbide (TiAlC),tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN),tantalum aluminum nitride (TaAlN), a combination thereof or othersuitable ceramals. The element ratio of the alloy, ceramet or ceramalcan be adjusted, and is not limited to those exemplified above.

The dummy gate DG1 has a work function. The work function of the gate Gmay be the same as or different from the work function of the dummy gateDG1. In practical applications, the work function and the distributionlocation of the dummy gate DG1 may be designed to meet the requirementsof device performance and device reliability.

The gate dielectric layer 222 is between the gate G and the substrate210 and between the dummy gate DG1 and the drift region 214. In someembodiments, the gate dielectric layer 222 includes a dielectricmaterial such as silicon oxide, silicon nitride, silicon oxynitride oranother suitable insulating material.

The interconnection line 250 is electrically connected to the dummy gateDG1 and configured to provide a voltage potential to the dummy gate DG1.The dummy gate DG1 receiving the voltage potential is configured to letdrain current pass near a surface of the drift region 214, and thus tosignificantly increase drain current and improve device performance whenthe transistor 50 is at on state. Moreover, the interconnection line 250and other interconnection lines (not shown), such as interconnectionlines respectively electrically connected to the source region SR andthe drain region DR, may be simultaneously formed, and thus there is noneed for extra process to form the interconnection line 250.

In some embodiments, the interconnection line 250 includes metal, alloy,ceramet, ceramal or a combination thereof, such as titanium (Ti),tantalum (Ta), tungsten (W), aluminum (Al), copper (Cu), molybdenum(Mo), platinum (Pt), titanium aluminum (TiAl), titanium nitride (TiN),tantalum nitride (TaN), titanium silicon nitride (TiSiN), titaniumcarbide (TiC), tantalum carbide (TaC), tantalum carbonitride (TaCN),molybdenum nitride (MoN), molybdenum oxynitride (MoON), ruthenium oxide(RuO₂), titanium aluminum nitride (TiAlN), a combination thereof orother suitable materials. In some embodiments, the gate G iselectrically connected to the dummy gate DG1, and thus both the gate Gand the dummy gate DG1 may receive a power supply voltage (Vcc).

In some embodiments, the transistor 50 further includes a protectivelayer (or called as spacer) 240. In some embodiments, the protectivelayer 240 is made of silicon oxide, silicon nitride, silicon oxynitrideor another suitable materials.

FIG. 6 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure. The difference between theembodiments of FIGS. 5 and 6 is that in FIG. 6, the transistor 60further includes an isolation region 260 in the drift region 214 andadjacent to the drain region DR. In some embodiments, the isolationregion 260 is not overlapped with the dummy gate DG1. The isolationregion 260 may be a shallow-trench isolation (STI) region or a fieldoxide (FOX) region. The transistor 60 can exhibit good devicereliability due to the presence of the isolation region 160 and gooddevice performance due to the presence of the dummy gate DG1 having thevoltage potential when the transistor 60 is at on state.

FIG. 7 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure. The difference between theembodiments of FIGS. 5 and 7 is that in FIG. 7, the gate G has a workfunction different from a work function of the dummy gate DG1. In someembodiments, the gate G and the dummy gate DG1 include metal, alloy,ceramet, ceramal or a combination thereof. The work function of the gateG and that of the dummy gate DG1 may be determined by composition andelement ratio. In some embodiments, the work function of the gate G issmaller than the work function of the dummy gate DG1 when the transistor70 is an n-channel transistor, and thus lateral drain field can beblocked through the dummy gate DG1 when the transistor 70 is at offstate. In some embodiments, the work function of the gate G is greaterthan the work function of the dummy gate DG1 when the transistor 70 is ap-channel transistor, and thus lateral drain field can be blockedthrough the dummy gate DG1 when the transistor 70 is at off state.Accordingly, the transistor 70 possesses good device performance andgood device reliability simultaneously. In addition, in the case of thesame device reliability, the transistor 50 may have a smaller devicesize compared to the transistor 30.

FIG. 8 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure. The difference between theembodiments of FIGS. 7 and 8 is that in FIG. 8, the transistor 80further includes another dummy gate DG2 over the drift region 214 andlaterally adjacent to the dummy gate DG1. The dummy gate DG2 isconfigured to help the dummy gate DG1 to alter drain current and blockdrain field. In some embodiments, the dummy gate DG2 is a floating dummygate. In some embodiments, the dummy gate DG2 is electrically connectedto the dummy gate DG1. In some embodiments, the dummy gate DG2 has awork function the same as or different from that of the dummy gate DG1.In practical applications, the distribution location in a top view, thevoltage potential when the transistor 80 is at on state and the workfunction of the dummy gates DG1, DG2 are tunable to meet requirements ofdevice performance and device reliability, and thus not limited to theembodiments exemplified in the specification. In addition, thetransistor may include three or more dummy gates.

FIG. 9 is a cross-sectional view of a transistor in accordance with someembodiments of the present disclosure. The transistor 90 includes asource region SR, a drain region DR, a channel region 212, a driftregion 214, a gate G, a dummy gate DG1 and a gate dielectric layer 222.The gate G has a work function different from a work function of thedummy gate DG1, and thus to block lateral drain field by the dummy gateDG1 when the transistor 90 is at off state, which results in highbreakdown voltage and good device reliability. In some embodiments, thework function of the gate G is smaller than the work function of thedummy gate DG1 when the transistor 90 is an re-channel transistor. Insome embodiments, the work function of the gate G is greater than thework function of the dummy gate DG1 when the transistor 90 is ap-channel transistor.

As mentioned above, each of the transistors 50, 60, 70, 80 can exhibitgood device performance because of the dummy gate DG1 having a voltagepotential at on state. In another aspect, each of the transistors 70,80, 90 can exhibit good device reliability because the work function ofthe gate G is different from that of the dummy gate DG1. It isnoteworthy that the device reliability of the transistors 70, 80, 90 canbe altered by changing the material of the dummy gate DG1, and thus itis not unfavorable to device size.

FIGS. 10A-10F are cross-sectional views at various stages ofmanufacturing a transistor in accordance with some embodiments of thepresent disclosure.

As shown in FIG. 10A, a substrate 210 having a drift region 214 and achannel region 212 is received. The drift region 214 and the channelregion 212 are in the substrate 210, and the channel region 212 isadjacent to the drift region 214. The drift region 214 is of a firstconductivity type, and the channel region 212 is of a secondconductivity type opposite to the first conductivity type. The driftregion 214 is acted as an extension of a drain region to be formedsubsequently. In some embodiments, the drift region 214 is formed byimplantation of the first conductive type dopants, and the channelregion 212 is formed by implantation of the second conductive typedopants. The formation of the channel region 212 may be prior or next tothe formation of the drift region 214.

As shown in FIG. 10B, a dielectric layer 220 and a gate layer 230 aresequentially formed over the substrate 210. In some embodiments, adielectric material and a gate material are sequentially blanketdeposited on the substrate 210 to form the dielectric layer 220 and thegate layer 230. In some embodiments, the dielectric material is blanketdeposited using a PVD process, a CVD process, a spin-on coating process,a thermal dry oxidation, a thermal wet oxidation or another formationprocess. In some embodiments, the gate material is blanket depositedusing a PVD process, a CVD process, an ALD process, a plating process, aspin-on coating process or another suitable formation process.

As shown in FIGS. 10B-10C, the gate layer 230 and the dielectric layer220 beneath the gate layer 230 are patterned to form the gate G, thepre-dummy gate PDG and the gate dielectric layer 222 over the substrate210. The gate G is overlapped with a portion of the channel region 212and a portion of the drift region 214. The pre-dummy gate PDG is overthe drift region 214 and laterally adjacent to the gate G. The gatedielectric layer 222 is between the gate G and the substrate 210 andbetween the pre-dummy gate PDG and the drift region 214. In someembodiments, the gate layer 230 and the dielectric layer 220 arepatterned using a photolithography/etching process or another suitablematerial removal process.

As shown in FIG. 10D, a protective layer (or called as spacer) 240 isformed covering sidewalls of the gate G and sidewalls of the pre-dummygate PDG. In some embodiments, a protective material is blanketdeposited covering the gate G, the pre-dummy gate PDG, the gatedielectric layer 222, the channel region 212 and the drift region 214,and a trimming process, such as an anisotropic dry etch process, is thenperformed on the protective material to form the protective layer 240.In some embodiments, the protective material is made of silicon oxide,silicon nitride, silicon oxynitride or another suitable materials.

After the protective layer 240 is formed, a source region SR and a drainregion DR are respectively formed in the channel region 212 and thedrain region 214, as shown in FIG. 10D. The source region SR and thedrain region DR are of the first conductivity type. In some embodiments,the first type dopants are implanted into a selective area of thechannel region 212 and a selective area of the drift region 214 to formthe source region SR and the drain region DR.

As shown in FIG. 10E, the pre-dummy gate PDG is removed to form a cavity230a confined by the protective layer 240. In some embodiments, thepre-dummy gate PDG is removed using a wet etching process, and theprotective layer 240 is not removed due to selectivity of the etchant.

As shown in FIG. 10F, a dummy gate DG1 is formed in the cavity 230 a. Insome embodiments, the dummy gate DG1 is formed by deposition, such asCVD process, a PVD process, an ALD process, a spin-on coating process oranother formation process. In some embodiments, the metal-containingmaterial includes metal, alloy, ceramet, ceramal or a combinationthereof.

In some embodiments, the method further includes forming aninterconnection line 250 electrically connected to the dummy gate DG1,as shown in FIG. 7. In some embodiments, before the interconnection line250 is formed, an inter-layer dielectric (ILD) (not shown) is formedcovering the source region SR, the drain region DR, the channel region212, the drift region 214, the gate G and the dummy gate DG1. The ILDmay be formed using a CVD process, a PVD process, an ALD process, aspin-on process or another suitable formation process. The ILD is thenpatterned to form an opening (not shown), and a conductive material isthen filled in the opening to form the interconnection line 250. In someembodiments, the ILD is patterned using a photolithography/etchingprocess, a laser drilling process or another suitable material removalprocess. In some embodiments, the conductive material is formed using aCVD process, a PVD process, an ALD process, a spin-on coating process oranother formation process.

According to some embodiments, a transistor includes a source region, achannel region, a drift region, a gate, a dummy gate, a gate dielectriclayer and an interconnection line. The source region of a firstconductivity type and the drain region of the first conductivity typeare in a substrate. The channel region of a second conductivity typeopposite to the first conductivity type is in the substrate andsurrounds the source region. The drift region of the first conductivitytype is beneath the drain region and extends toward the channel region.The gate is over the substrate and overlapped with a portion of thechannel region and a portion of the drift region. The dummy gate is overthe drift region and laterally adjacent to the gate. The gate dielectriclayer is between the gate and the substrate and between the dummy gateand the drift region. The interconnection line is electrically connectedto the dummy gate and configured to provide a voltage potential to thedummy gate.

According to some embodiments, a transistor includes a source region, achannel region, a drift region, a gate, a dummy gate and a gatedielectric layer. The source region of a first conductivity type and thedrain region of the first conductivity type are in a substrate. Thechannel region of a second conductivity type opposite to the firstconductivity type is in the substrate and surrounds the source region.The drift region of the first conductivity type is beneath the drainregion and extends toward the channel region. The gate is over thesubstrate and overlapped with a portion of the channel region and aportion of the drift region. The dummy gate is over the drift region andlaterally adjacent to the gate, in which the gate has a work functiondifferent from a work function of the dummy gate. The gate dielectriclayer is between the gate and the substrate and between the dummy gateand the drift region.

According to some embodiments, a substrate having a drift region in thesubstrate and a channel region in the substrate and adjacent to thedrift region is received. The drift region is of a first conductivitytype, and the channel region is of a second conductivity type oppositeto the first conductivity type. A gate, a pre-dummy gate and a gatedielectric layer are formed over the substrate. The gate is overlappedwith a portion of the channel region and a portion of the drift region.The pre-dummy gate is over the drift region and laterally adjacent tothe gate. The gate dielectric layer is between the gate and thesubstrate and between the pre-dummy gate and the drift region. Aprotective layer is formed covering sidewalls of the gate and sidewallsof the pre-dummy gate. A source region and a drain region arerespectively formed in the channel region and the drift region. Thesource region and the drain region are of the first conductivity type.The pre-dummy gate is removed to form a cavity. A dummy gate is formedin the cavity.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

1. (canceled)
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 5. (canceled) 6.(canceled)
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 15. Atransistor, comprising: a source region of a first conductivity type anda drain region of the first conductivity type in a substrate; a channelregion of a second conductivity type opposite to the first conductivitytype in the substrate and surrounding the source region; a drift regionof the first conductivity type beneath the drain region and extendingtoward the channel region; a gate over the substrate and overlapped witha portion of the channel region and a portion of the drift region; ametal-containing material over the drift region and laterally adjacentto the gate, wherein the gate has a work function different from a workfunction of the metal-containing material and the gate is electricallyconnected to the metal-containing material; and a gate dielectric layerbetween the gate and the substrate and between the metal-containingmaterial and the drift region.
 16. The transistor of claim 15, whereinthe work function of the gate is smaller than the work function of themetal-containing material when the transistor is an n-channeltransistor.
 17. The transistor of claim 15, wherein the work function ofthe gate is greater than the work function of the metal-containingmaterial when the transistor is a p-channel transistor.
 18. (canceled)19. (canceled)
 20. (canceled)
 21. (canceled)
 22. (canceled) 23.(canceled)
 24. (canceled)
 25. The transistor of claim 15, wherein themetal-containing material comprises titanium aluminum (TiAl), tantalumaluminum (TaAl), tungsten aluminum (WAl), zirconium aluminum (ZrAl),hafnium aluminum (HfAl), or a combination thereof.
 26. The transistor ofclaim 15, wherein the metal-containing material comprises titaniumnitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN),tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN),titanium carbide (TiC), tantalum carbide (TaC), or a combinationthereof.
 27. The transistor of claim 15, wherein the metal-containingmaterial comprises titanium aluminum carbide (TiAlC), tantalum aluminumcarbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum aluminumnitride (TaAlN), or a combination thereof.
 28. (canceled)